Analysis and application of improved feedthrough logic

Continuous technology scaling and increased frequency of operation of VLSI circuits leads to increase in power density which raises thermal management problem. Therefore design of low power VLSI circuit technique is a challenging task without sacrificing its performance. This thesis presents the design of a low power dynamic circuit using a new CMOS domino logic family called feedthrough (FTL) logic. Dynamic logic circuits are more significant because of its faster speed and lesser transistor requirement as compared to static CMOS logic circuits. The need for faster circuits compels designers to use FTL as compared static and domino CMOS logic and the requirement of output inverter for cascading of various logic blocks in domino logic are eliminated in the proposed design. The proposed circuit for low power (LP-FTL) improves dynamic power consumption as compared to the existing FTL and to further improve its speed we propose another circuit (HS-FTL). This logic family improves speed at the cost of dynamic power consumption and area. Proposed modified FTL circuit families provide better PDP as compared to the existing FTL. Simulation results of both the proposed circuit using 0.18 µm, 1.8 V CMOS process technology indicate that the LP-FTL structure reduces the dynamic power approximately by 42% and the HS-FTL structure achieves a speed up- 1.4 for 10-stage of inverters and 8-bit ripple carry adder in comparison to existing FTL logic. Furthermore, we present various circuit design techniques to improve noise tolerance of the proposed FTL logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (average noise threshold energy) metric is used for the analysis of noise tolerance of proposed FTL. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at 0.18-µm, 1.8 V CMOS process technology show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the nanometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity

Hardware Security: Addressing challenges through PUF and recycled IC detection

Globalization of semiconductor supply/design chain has led to several hardware security problems. The different stages of chip design, fabrication, packaging and testing are performed in different countries. The well-known hardware security problems are: - different types of side channel attacks (SCA), counterfeiting, hardware Trojans, and IP (Intellectual Property) violations. Counterfeit parts are not reliable and using these parts in critical applications like avionics and healthcare would create catastrophic consequences. The two major sources of counterfeit parts are: - counterfeit parts coming from unauthorized production from untrusted foundries and recycled parts from the obsolete electronic equipment. In this dissertation, we mainly focus on solving the issue of counterfeiting of both the kinds mentioned above. Physical Unclonable Function (PUF) is promising hardware security primitive which is helpful in solving few hardware security problems like counterfeiting and IP violations. PUF circuits are equally useful in generating the keys for cryptographic applications. PUF circuits exploit the inherent process variation occurring during manufacturing of chips to generate response (input) for a given challenge (output). The input-output pair is called Challenge Response pair (CRP). The quality of CRP’s generated by PUF is measured by using quality factors. The widely accepted quality metrics are: - reliability, uniqueness and uniformity. The PUF circuits are highly helpful in solving the problem of counterfeit parts coming from untrusted foundries. The quality of PUF circuit with better quality metrics is necessary to address the counterfeiting. In this dissertation we propose novel PUF circuits with better quality metrics, particularly reliability. Reliability of CRPs is very important in identification of the device and also in cryptographic key generation. In the process of designing PUF, we explore the possibility of using circuits with different logic styles which can pick up better process variation during manufacturing. The impact of process variation on threshold voltage and other factors are examined in designing PUFs with better reliability. In this research, we propose a PUF circuit with Feedthrough logic (FTL) that enhances the PUF performance as compared to conventional CMOS logic based circuits. The CRP is resilient against temperature and other environmental variations. We also propose aging resistant PUF circuit based on FTL by using threshold voltage dependent reduced supply voltage technique. Overall, we present the novel PUF design for better reliability and resilient against environmental and aging effects. The proposed novel PUF designs consume less power in comparison with existing PUF circuits. Secondly, we also address the problem of counterfeiting coming from recycling of parts from obsolete electronic equipment. We propose an on-chip lightweight ring oscillator (RO) sensor that is designed using modified pseudo NMOS logic style for detection of recycled IC. The proposed sensor is able to detect the recycled chips, even though chip is used for a few days. In this dissertation, we have addressed the problem of counterfeit parts both from the untrusted foundry (counterfeiting at source) and counterfeits from recycling of electronic equipment